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Gigabit Ethernet Transceiver Chip Preliminary Technical Data
HDMP-1636 Transceiver HDMP-1646 Transceiver Features
* IEEE 802.3z Gbit Ethernet Compatible, Supports 1250 MBd Gigabit Ethernet * Based on X3T11 "10 Bit Specification" * Low Power Consumption * Transmitter and Receiver Functions Incorporated onto a Single IC * Two Package Sizes Available: - 10 mm PQFP (HDMP-1636) - 14 mm PQFP (HDMP-1646) * 10-Bit Wide Parallel TTL Compatible I/Os * Single +3.3 V Power Supply * 5-Volt Tolerant I/Os * 2 KV ESD Protection
provides complete Serialize/ Deserialize for copper transmission, incorporating both the Gigabit Ethernet transmit and receive functions into a single device. This chip is used to build a high speed interface (as shown in Figure 1) while minimizing board space, power and cost. It is compatible with the IEEE 802.3z specification. The transmitter section accepts 10-bit wide parallel TTL data and multiplexes this data into a high speed serial data stream. The parallel data is expected to be 8B/10B encoded data, or equivalent. This parallel data is latched into the input register of the transmitter section on the rising edge of the 125 MHz reference clock (used as the transmit byte clock). The transmitter section's PLL locks to this user supplied 125 MHz byte clock. This clock is then multiplied by 10, to generate the 1250 MHz serial signal clock used to generate the high speed output. The high speed outputs are capable of interfacing directly to copper cables for electrical transmission or to a separate fiber optic module for optical transmission.
Applications
* 1250 MBd Gigabit Ethernet Interface * High Speed Proprietary Interface * Backplane Serialization * Bus Extender
The receiver section accepts a serial electrical data stream at 1250 MBd and recovers the original 10-bit wide parallel data. The receiver PLL locks onto the incoming serial signal and recovers the high speed serial clock and data. The serial data is converted back into 10-bit parallel data, recognizing the 8B/10B comma character to establish byte alignment. The recovered parallel data is presented to the user at TTL compatible outputs. The receiver section also recovers two 62.5 MHz receiver byte clocks which are 180 degrees out of phase with each other. The parallel data is properly aligned with the rising edge of alternating clocks. For test purposes, the transceiver provides for on-chip local loopback functionality, controlled through an external input pin. Additionally, the byte
Description
The HDMP-1636/46 transceiver is a single silicon bipolar integrated circuit packaged in a plastic QFP package. It provides a low-cost, low-power physical layer solution for 1250 MBd Gigabit Ethernet or proprietary link interfaces. It
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HDMP-16x6 TRANSMITTER SECTION SERIAL DATA OUT PLL PROTOCOL DEVICE
PLL RECEIVER SECTION BYTSYNC SERIAL DATA IN
REFCLK ENBYTSYNC
Figure 1. Typical Application Using the HDMP-16x6.
INPUT LATCH
DATA BYTE TX[0-9]
FRAME MUX
OUTPUT SELECT INTERNAL LOOPBACK
DOUT
LOOPEN
TXCAP0 TXCAP1
TX PLL/CLOCK GENERATOR
INTERNAL TX CLOCKS
INPUT SELECT
DIN
REFCLK RXCAP0 RXCAP1 RBC0 RBC1 RX PLL/CLOCK RECOVERY
OUTPUT DRIVER
DATA BYTE RX[0-9]
FRAME DEMUX AND BYTE SYNC
INTERNAL RX CLOCKS INPUT SAMPLER
BYTSYNC
ENBYTSYNC
Figure 2. HDMP-16x6 Transceiver Block Diagram.
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synchronization feature may be disabled. This may be useful in proprietary applications which use alternative methods to align the parallel data.
HDMP-1636/46 Block Diagram
The HDMP-1636/46 was designed to transmit and receive 10-bit wide parallel data over a single high-speed line. The parallel data applied to the transmitter is expected to be encoded per the Gigabit Ethernet specification, which uses an 8B/10B encoding scheme with special reserve characters for link management purposes. In order to accomplish this task, the HDMP-1636/46 incorporates the following: * TTL Parallel I/O's * High Speed Phase Lock Loops * Clock Generation/Recovery Circuitry * Parallel to Serial Converter * High Speed Serial Clock and Data Recovery Circuitry * Comma Character Recognition Circuitry * Byte Alignment Circuitry * Serial to Parallel Converter INPUT LATCH The transmitter accepts 10-bit wide TTL parallel data at inputs TX[0..9]. The user-provided reference clock signal, REFCLK, is also used as the transmit byte clock. The TX[0..9] and REFCLK signals must be properly aligned, as shown in Figure 3.
TX PLL/CLOCK GENERATOR The transmitter Phase Lock Loop and Clock Generator (TX PLL/ CLOCK GENERATOR) block is responsible for generating all internal clocks needed by the transmitter section to perform its functions. These clocks are based on the supplied reference byte clock (REFCLK). REFCLK is used as both the frequency reference clock for the PLL and the transmit byte clock for the incoming data latches. It is expected to be 125 MHz and properly aligned to the incoming parallel data (see Figure 3). This clock is then multiplied by 10 to generate the 1250 MHz clock necessary for the high speed serial outputs. FRAME MUX The FRAME MUX accepts the 10bit wide parallel data from the INPUT LATCH. Using internally generated high speed clocks, this parallel data is multiplexed into the 1250 MBd serial data stream. The data bits are transmitted sequentially, from the least significant bit (TX[0]) to the most significant bit (TX[9]). OUTPUT SELECT The OUTPUT SELECT block provides for an optional internal loopback of the high speed serial signal, for testing purposes. In normal operation, LOOPEN is set low and the serial data stream is placed at +/- DOUT. When wrap-mode is activated by setting
LOOPEN high, the +/- DOUT pins are held static at logic 1 and the serial output signal is internally wrapped to the INPUT SELECT box of the receiver section. INPUT SELECT The INPUT SELECT block determines whether the signal at +/- DIN or the internal loop-back serial signal is used. In normal operation, LOOPEN is set low and the serial data is accepted at +/- DIN. When LOOPEN is set high, the high speed serial signal is internally looped-back from the transmitter section to the receiver section. This feature allows for loop back testing exclusive of the transmission medium. RX PLL/CLOCK RECOVERY The RX PLL/CLOCK RECOVERY block is responsible for frequency and phase locking onto the incoming serial data stream and recovering the bit and byte clocks. An automatic locking feature allows the Rx PLL to lock onto the input data stream without external controls. It does this by continually frequency locking onto the 125 MHz clock, and then phase locking onto the input data stream. An internal signal detection circuit monitors the presence of the input, and invokes the phase detection as the data stream appears. Once bit locked, the receiver generates the high speed sampling clock at 1250 MHz for the input sampler, and recovers the two 62.5 Mhz
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receiver byte clocks (RBC1/RBC0). These clocks are 180 degrees out of phase with each other, and are alternately used to clock the 10-bit parallel output data. INPUT SAMPLER The INPUT SAMPLER is responsible for converting the serial input signal into a re-timed serial bit stream. In order to accomplish this, it uses the high speed serial clock recovered from the RX PLL/CLOCK RECOVERY block. This serial bit stream is sent to the FRAME DEMUX and BYTE SYNC block.
FRAME DEMUX AND BYTE SYNC The FRAME DEMUX AND BYTE SYNC block is responsible for restoring the 10-bit parallel data from the high speed serial bit stream. This block is also responsible for recognizing the comma character (or a K28.5 character) of positive disparity (0011111xxx). When recognized, the FRAME DEMUX AND BYTE SYNC block works with the RX PLL/CLOCK RECOVERY block to properly align the receive byte clocks to the parallel data. When a comma character is detected and realignment of the receiver byte clocks (RBC1/RBC0) is necessary, these clocks are stretched, not slivered, to the
next possible correct alignment position. These clocks will be fully aligned by the start of the second 2-byte ordered set. The second comma character received shall be aligned with the rising edge of RBC1. Comma characters should not be transmitted in consecutive bytes to allow the receiver byte clocks to maintain their proper recovered frequencies. OUTPUT DRIVERS The OUTPUT DRIVERS present the 10-bit parallel recovered data byte properly aligned to the receive byte clocks (RBC1/RBC0), as shown in Figure 5. These output data buffers provide TTL compatible signals.
HDMP-1636/46 (Transmitter Section)
Timing Characteristics TA = 0C to +60C, VCC = 3.15 V to 3.45 V Symbol Parameter tsetup Setup Time thold Hold Time [1] t_txlat Transmitter Latency
Units nsec nsec nsec bits
Min. 2 1
Typ.
Max.
TBD TBD
Note: 1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered by the rising edge of the transmit byte clock, REFCLK) and the transmission of the first serial bit of that parallel word (defined by the rising edge of the first bit transmitted).
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,,, ,, ,,
REFCLK TX[0]-TX[9] DATA DATA DATA DATA DATA tSETUP tHOLD
1.4 V
2.0 V
0.8 V
Figure 3. Transmitter Section Timing.
DOUT
TX[0]-TX[9]
REFCLK
,, ,,
DATA BYTE A T5 T6 T7 T8 T9 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T0 t_TXLAT DATA BYTE B
DATA BYTE B
T1
T2
T3
T4
T5
DATA BYTE C
1.4 V
Figure 4. Transmitter Latency.
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HDMP-1636/46 (Receiver Section)
Timing Characteristics TA = 0C to +70C, VCC = 3.15 V to 3.45 V Symbol Parameter [1,2] b_sync Bit Sync Time tvalid_before Time Data Valid Before Rising Edge of RBC tvalid_after Time Data Valid After Rising Edge of RBC tduty RBC Duty Cycle tA-B Rising Edge Time Difference [3] t_rxlat Receiver Latency
Units bits nsec nsec % nsec nsec bits
Min. 2.5 1.5 40 7.5
Typ. TBD TBD 7.9 22.4 28
Max. 2500
60 8.5
Notes: 1. This is the recovery time for input phase jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3. 2. Tested using CPLL = 0.1 F. 3. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word (defined as the first edge of the first serial) and the clocking out of that parallel word (defined by the rising edge of the receive byte clock, either RBC1 or RBC0).
,,,,,,, ,,
tvalid_before tvalid_after RBC1 1.4 V 2.0 V 0.8 V 2.0 V RX[0]-RX[9] K28.5 DATA DATA DATA DATA BYTSYNC 0.8 V RBC0 1.4 V tA-B
Figure 5. Receiver Section Timing.
Figure 6. Receiver Latency.
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HDMP-1636/46 (TRx) Absolute Maximum Ratings
TA = 25C, except as specified. Operation in excess of any one of these conditions may result in permanent damage to this device. Symbol VCC VIN,TTL VIN,HS_IN IO,TTL Tstg Tj Parameter Supply Voltage TTL Input Voltage HS_IN Input Voltage TTL Output Source Current Storage Temperature Junction Operating Temperature Units V V V mA C C Min. -0.5 -0.7 2.0 -40 0 Max. 5.0 VCC + 0.7 VCC 13 +130 +130
HDMP-1636/46 (TRx) Guaranteed Operating Rates
TA = 0C to +70C, VCC = 3.15 V to 3.45 V Parallel Clock Rate (MHz) Serial Baud Rate (MBaud) Min. Max. Min. Max. 124.0 126.0 1240 1260
HDMP-1636/46 (TRx) Transceiver Reference Clock Requirements
TA = 0C to +70C, VCC = 3.15 V to 3.45 V Symbol Parameter f Nominal Frequency (for Gigabit Ethernet Compliance) Ftol Frequency Tolerance Symm Symmetry (Duty Cycle) Unit MHz ppm % Min. -100 40 Typ. 125 Max. +100 60
HDMP-1636/46 (TRx) DC Electrical Specifications
TA= 0C to +70C, VCC = 3.15 V to 3.45 V Symbol Parameter VIH,TTL TTL Input High Voltage Level, Guaranteed High Signal for All Inputs VIL,TTL TTL Input Low Voltage Level, Guaranteed Low Signal for All Inputs VOH,TTL TTL Output High Voltage Level, IOH = -400 A VOL,TTL TTL Output Low Voltage Level, IOL = 1 mA IIH,TTL Input High Current (Magnitude), VIN = VCC IIL-TTL Input Low Current (Magnitude), VIN = 0 Volts [1,2] ICC,TRx Transceiver VCC Supply Current, TA = 25C Unit V V V V A A mA Min. 2 0 2.2 0 0.003 -366 205 Typ. Max. VCC 0.8 VCC 0.6 40 -600
Notes: 1. Measurement Conditions: Tested sending 1250 MBd PRBS 27-1 sequence from a serial BERT with both DOUT outputs biased with 150 resistors. 2. Typical specified with VCC = 3.3 volts, maximum specified with VCC = 3.45 volts.
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HDMP-1636/46 (TRx) AC Electrical Specifications
TA = 0C to +70C, VCC = 3.15 V to 3.45 V Symbol Parameter tr,TTLin Input TTL Rise Time, 0.8 to 2.0 Volts tf,TTLin Input TTL Fall Time, 2.0 to 0.8 Volts tr,TTLout Output TTL Rise Time, 0.8 to 2.0 Volts, 10 pF Load tf,TTLout Output TTL Fall Time, 2.0 to 0.8 Volts, 10 pF Load trs,HS_OUT HS_OUT Single-Ended (+DOUT) Rise Time tfs,HS_OUT HS_OUT Single-Ended (+DOUT) Fall Time trd,HS_OUT HS_OUT Differential Rise Time tfd,HS_OUT HS_OUT Differential Fall Time VIP,HS_IN HS_IN Input Peak-to-Peak Differential Voltage VOP,HS_OUT[1] HS_OUT Output Peak-to-Peak Differential Voltage
Note: 1. Output Peak-to-Peak Differential Voltage specified as DOUT+ minus DOUT-.
Units nsec nsec nsec nsec psec psec psec psec mV mV
Min.
85 85 85 85 200 1200
Typ. 2 2 1.5 1.1 TBD TBD
Max.
1200 1580
2.4 2.4 327 327 327 327 2000 2200
22.0680 ns
Yaxis = 400 mV/DIV
a. Differential HS_OUT Output (Dout+ Minus Dout-).
22.0680 ns
Yaxis = 200 mV/DIV
b. Single-Ended HS_OUT Output (Dout+). Eye Diagrams of the High-Speed Serial Outputs from the HDMP-1636/46 as Captured on the HP 83480A Digital Communications Analyzer. Tested with PRBS = 27-1. Figure 7. Transmitter DOUT Eye Diagrams.
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HDMP-1636/46 (Transmitter Section) Output Jitter Characteristics
TA = 0C to +70C, VCC = 3.15 V to 3.45 V Symbol Parameter [1] RJ Random Jitter at DOUT, the High Speed Electrical Data Port, specified as 1 sigma deviation of the 50% crossing point (RMS) DJ[1] Deterministic Jitter at DOUT, the High Speed Electrical Data Port (pk-pk) Units ps ps Typ. 8 15
Note: 1. Defined by Fibre Channel Specification X3.230-1994 FC-PH Standard, Annex A, Section A.4 and tested using measurement method shown in Figure 8.
HP70311A CLOCK SOURCE
HP70841B PATTERN GENERATOR* 0000011111 + DATA - DATA 1.25 GHz HP70311A CLOCK SOURCE +DOUT BIAS TEE -DOUT 125 MHz TRIGGER CH1 CH2
HP70841B PATTERN GENERATOR
+K28.5, -K28.5
HP83480A OSCILLOSCOPE
1.25 GHz
+ DATA - DATA
HP83480A OSCILLOSCOPE
DIVIDE BY 10 CIRCUIT (DUAL OUTPUT) DIVIDE BY 2 CIRCUIT TRIGGER CH1 CH2
HDMP-1636 REFCLK LOOPEN
+DOUT VARIABLE DELAY TTL
-DOUT
* PATTERN GENERATOR PROVIDES A DIVIDE BY 10 FUNCTION. 1.4 V
Tx[0..9]
HDMP-1636
125 MHz REFCLK Tx[0..9]
-DIN +DIN
ENBYTSYNC LOOPEN Rx[0..9]
0011111000 (STATIC K28.7)
a. Block Diagram of RJ Measurement Method. Figure 8. Transmitter Jitter Measurement Method.
b. Block Diagram of DJ Measurement Method.
HDMP-1636/46 (TRx) Thermal and Power Temperature Characteristics
TA = 0C to +70C, VCC = 3.15 V to 3.45 V Symbol Parameter [1,2] PD,TRx Transceiver Power Dissipation, Outputs Open, Parallel Data has 5 Ones and 5 Zeroes PD,TRx[1,2,3] Transceiver Power Dissipation, Outputs Connected per Recommended Bias Terminations with Idle Pattern [4] jc Thermal Resistance, Junction to Case HDMP-1636 HDMP-1646 Units mW mW C/Watt Typ. 630 685 10 7 Max. 850 900
Notes: 1. PD is obtained by multiplying the max VCC by the max ICC and subtracting the power dissipated outside the chip at the high speed bias resistors. 2. Typical value specified with VCC = 3.3 volts, maximum value specified with VCC = 3.45 volts. 3. Specified with high speed outputs biased with 150 resistors and receiver TTL outputs driving 10 pF loads. 4. Based on independent package testing by HP. ja for these devices is 48C/Watt for the HDMP-1636 and 44C/Watt for the HDMP-1646. ja is measured on a standard 3x3" FR4 PCB in a still air environment. To determine the actual junction temperature in a given application, use the value as described as follows: Tj = TC + (jc x Pd), where TC is the case temperature measured on the top center of the package and PD is the power being dissipated.
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I/O Type Definitions
I/O Type I-TTL O-TTL HS_OUT HS_IN C S Definition Input TTL, Floats High When Left Open Output TTL High Speed Output, ECL Compatible High Speed Input External Circuit Node Power Supply or Ground
HDMP-1636/46 (TRx) Pin Input Capacitance
Symbol CINPUT
O_TTL
VCC_TTL VCC_TTL
Parameter Input Capacitance on TTL Input Pins
Units pF
I_TTL
Typ. 1.6
Max.
R
R
VCC_TX or VCC_RX
R
R
R VBB 1.4 V
GND GND_TTL ESD PROTECTION ESD PROTECTION GND_TTL
Figure 9. O-TTL and I-TTL Simplified Circuit Schematic.
HS_OUT
VCC_TXHS VCC_TXECL VCC_TX +DOUT RPAD 150 -DOUT RPAD 150 Zo = 75 0.01 GND ESD
PROTECTION
HS_IN
VCC_RXHS + - R R Zo = 75 0.01 +DIN + -
VCC_RX
-DIN GND ESD
PROTECTION
150 GND_TXHS GND_RXHS
Figure 10. HS_OUT and HS_IN Simplified Circuit Schematic. Notes: 1. HS_IN inputs should never be connected to ground as permanent damage to the device may result. 2. The optional series padding resistors (Rpad) help dampen load reflections. Typical Rpad values for mismatched loads range between 25-75 .
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-DOUT VCC_TXECL
GND VCC_RX GND_RXHS
GND_TXHS VCC_TXHS +DOUT
VCC_RXHS +DIN
VCC_RXHS
-DIN GND_RXA
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 GND_TXTTL TX[0] TX[1] TX[2] VCC_TXTTL TX[3] TX[4] TX[5] TX[6] VCC_TXTTL TX[7] TX[8] TX[9] GND_TXTTL GND_TXA TXCAP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 RXCAP0 BYTSYNC GND_RXTTL RX[0] RX[1] RX[2] VCC_RXTTL RX[3] RX[4] RX[5] RX[6] VCC_RXTTL RX[7] RX[8] RX[9] GND_RXTTL
VCC_RXA RXCAP1
VCC_TX
HDMP-16x6 xxxx-x Rz.zz S YYWW
42 41 40 39 38 37 36 35 34 33
N/C* N/C*
VCC_RX ENBYTSYNC GND
xxxx-x = WAFER LOT NUMBER-BUILD NUMBER Rzz.zz = DIE REVISION S = SUPPLIER CODE YYWW = DATE CODE (YY = YEAR, WW = WORK WEEK) COUNTRY = COUNTRY OF MANUFACTURE (MARKED ON BACK OF DEVICE)
Figure 11. HDMP-1636/46 (TRx) Package Layout and Marking, Top View. *Note: Pins 26 and 27 are designated as "no connect" pins and must be left unconnected.
RBC0 GND_RXTTL
VCC_RXTTL RBC1
TXCAP0 VCC_TXA LOOPEN
VCC_TX GND REFCLK
VCC_RX
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TRx I/O Definition
Name BYTSYNC Pin 47 Signal Byte Sync Output: An active high output. Used to indicate detection of a comma character (0011111XXX). It is only active when ENBYTSYNC is enabled. HS_IN Serial Data Inputs: High-speed inputs. Serial data is accepted from the DIN inputs when LOOPEN is low. HS_OUT Serial Data Outputs: High-speed outputs. These lines are active when LOOPEN is set low. When LOOPEN is set high, these outputs are held static at logic 1. I-TTL Enable Byte Sync Input: When high, turns on the internal byte sync function to allow clock synchronization to a comma character, (0011111XXX). When the line is low, the function is disabled and will not reset registers and clocks, or strobe the BYTSYNC line. S Logic Ground: Normally 0 volts. This ground is used for internal PECL logic. It should be isolated from the noisy TTL ground as well as possible. S S S Analog Ground: Normally 0 volts. Used to provide a clean ground plane for the receiver PLL and high-speed analog cells. Ground: Normally 0 volts. TTL Receiver Ground: Normally 0 volts. Used for the TTL output cells of the receiver section. Analog Ground: Normally 0 volts. Used to provide a clean ground plane for the PLL and high-speed analog cells. Ground: Normally 0 volts. TTL Transmitter Ground: Normally 0 volts. Used for the TTL input cells of the transmitter section. Loopback Enable Input: When set high, the high-speed serial signal is internally wrapped from the transmitter's serial loopback outputs back to the receiver's loopback inputs. Also, when in loopback mode, the DOUT outputs are held static at logic 1. When set low, DOUT outputs and DIN inputs are active. Receiver Byte Clocks: The receiver section recovers two 62.5 MHz receive byte clocks. These two clocks are 180 degrees out of phase. The receiver parallel data outputs are alternately clocked on the rising edge of these clocks. The rising edge of RBC1 aligns with the output of the comma character (for byte alignment) when detected. Reference Clock and Transmit Byte Clock: A 125 MHz clock supplied by the host system. The transmitter section accepts this signal as the frequency reference clock. It is multiplied by 10 to generate the serial bit clock and other internal clocks. The transmit side also uses this clock as the transmit byte clock for the incoming parallel data TX[0]..TX[9]. It also serves as the reference clock for the receive portion of the transceiver. These pins are factory test pins and must be left unconnected. Type O-TTL
-DIN +DIN -DOUT +DOUT ENBYTSYNC
52 54 61 62 24
GND
GND_RXA GND_RXHS GND_RXTTL
21 25 58 51 56 32 33 46 15 64 1 14 19
GND_TXA GND_TXHS GND_TXTTL LOOPEN
S S S I-TTL
RBC1 RBC0
30 31
O-TTL
REFCLK
22
I-TTL
N/C
26,27
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TRx I/O Definition (cont'd.)
Name RX[0] RX[1] RX[2] RX[3] RX[4] RX[5] RX[6] RX[7] RX[8] RX[9] RXCAP0 RXCAP1 TX[0] TX[1] TX[2] TX[3] TX[4] TX[5] TX[6] TX[7] TX[8] TX[9] TXCAP1 TXCAP0 VCC_RX Pin 45 44 43 41 40 39 38 36 35 34 48 49 2 3 4 6 7 8 9 11 12 13 16 17 23 28 57 50 53 55 29 37 42 20 59 18 60 Type O-TTL Signal Data Outputs: One 10 bit data byte. RX[0] is the first bit received. RX[0] is the least significant bit.
C I-TTL
Loop Filter Capacitor: A loop filter capacitor for the internal PLL must be connected across the RXCAP0 and RXCAP1 pins. (typical value = 0.1 F). Data Inputs: One 10 bit, 8B/10B-encoded data byte. TX[0] is the first bit transmitted. TX[0] is the least significant bit.
C S
VCC_RXA VCC_RXHS
S S
VCC_RXTTL
S
Loop Filter Capacitor: A loop filter capacitor must be connected across the TXCAP1 and TXCAP0 pins (typical value = 0.1 F). Logic Power Supply: Normally 3.3 volts. Used for internal receiver PECL logic. It should be isolated from the noisy TTL supply as well as possible. Analog Power Supply: Normally 3.3 volts. Used to provide a clean supply line for the PLL and high-speed analog cells. High-Speed Supply: Normally 3.3 volts. Used only for the high-speed receiver cell (HS_IN). Noise on this line should be minimized for best operation. TTL Power Supply: Normally 3.3 volts. Used for all TTL receiver output buffer cells. Logic Power Supply: Normally 3.3 volts. Used for internal transmitter PECL logic. It should be isolated from the noisy TTL supply as well as possible. Analog Power Supply: Normally 3.3 volts. Used to provide a clean supply line for the PLL and high-speed analog cells. High-Speed ECL Supply: Normally 3.3 volts. Used only for the last stage of the high-speed transmitter output cell (HS_OUT) as shown in Figure 10. Due to high current transitions, this VCC should be well bypassed to a ground plane. High-Speed Supply: Normally 3.3 volts. Used by the transmitter side for the high-speed circuitry. Noise on this line should be minimized for best operation. TTL Power Supply: Normally 3.3 volts. Used for all TTL transmitter input buffer cells.
VCC_TX VCC_TXA VCC_TXECL
S S S
VCC_TXHS VCC_TXTTL
63 5 10
S S
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VCC* VCC
CPLLR
GND_TXTTL
RXCAP0 GND_RXTTL
VCC_TXTTL VCC_RXTTL VCC
TOP VIEW
VCC_TXTTL GND_TXTTL GND_TXA TXCAP0 VCC_TXA VCC_RX VCC_TX GND VCC_RXTTL GND_RXTTL VCC_RX VCC_RXTTL
TXCAP1
CPLLT
GND_RXTTL
power supply pins of the HDMP-1636/46 as shown on the schematic of Figure 12. All bypass chip capacitors are 0.1 F. The VCC_RXA and VCC_TXA pins are the analog power supply pins for the PLL sections. The voltage into these pins should be clean with minimum noise. The PLL loop filter capacitors and their pin locations are also shown on Figure 12. Notice that only two capacitors are required: CPLLT for the transmitter and CPLLR for the receiver. Nominal capacitance is 0.1 F. The voltage across the capacitors is on the order of 1 volt, so the capacitor can be a low voltage type and physically small. The PLL capacitors are placed physically close to the appropriate pins on the HDMP1636/46. Keeping the lines short will prevent them from picking up stray noise from surrounding lines or components.
GND_TXHS VCC_TXHS
VCC_TXECL VCC_TX
VCC_RXHS
GND VCC_RX GND_RXHS
VCC_RXHS
VCC* * SUPPLY VOLTAGE INTO VCC_RXA AND VCC_TXA SHOULD BE FROM A LOW NOISE SOURCE. ALL BYPASS CAPACITORS AND PLL FILTER CAPACITORS ARE 0.1 F.
GND
GND_RXA
VCC_RXA
RXCAP1
Figure 12. Power Supply Bypass.
Start-up Procedure: The transceiver start-up procedure(s) use the following conditions: VCC = +3.3 V 5% and REFCLK = 125 MHz 100 ppm. After the above conditions have been met, apply valid data using a balanced code such as 8B/10B. Frequency lock occurs within 500 s. After frequency lock, phase lock occurs within 2500 bit times.
Transceiver Power Supply Bypass and Loop Filter Capacitors
Bypass capacitors should be liberally used and placed as close as possible to the appropriate
PRE-RELEASE PRODUCT DISCLAIMER: This product is in development at the Hewlett-Packard CSSD in San Jose, California. Until HewlettPackard releases this product for general sales, HP reserves the right to alter specifications, features, capabilities, functions, manufacturing release dates, and even general availability of the product at any time.
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Package Information
Item Package Material Lead Finish Material Lead Finish Thickness Lead Coplanarity Details Plastic 85% Tin, 15% Lead 300-800 m HDMP-1636 0.08 mm max HDMP-1646 0.10 mm max
Mechanical Dimensions
PIN #1 ID
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 48 47 46 45 44 43 42 41 40
HDMP-16x6
A1
A2
TOP VIEW 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 B1 A1 A2 B2 B3
B4
B5
C1
C3
C2 ALL DIMENSIONS ARE IN MILLIMETERS. PART NUMBER HDMP-1636 HDMP-1646 TOLERANCE A1 10.00 14.00 A2 13.20 17.20 B1 0.22 0.35 B2 0.50 0.80 B3 0.60 0.88 B4 0.17 0.17 B5 0.25 0.25 C1 2.00 2.00 + 0.10/ - 0.05 C2 0.25 MIN. 0.25 MAX. C3 2.45 2.35 MAX.
0.10 0.25 0.05 BASIC + 0.15/ MAX. - 0.10
Figure 13. Mechanical Dimensions of HDMP-1636/46.
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